1 June 2012
SAN JOSE, Calif. — The tyrannical mistress that is the march of electronics innovation has pushed engineering teams to build more products in parallel–crafting software code to run on hardware that's being developed in parallel. It's an extraordinary feat that's not without perils.
EDA companies (which will gather next week for the Design Automation Conference) have worked for more than a decade to minimize those perils. In 2011, Cadence Design Systems unveiled its Virtual Systems Platform (VSP) in conjunction with Rapid Prototyping Platform (RPP) (a tool for FPGAs).
VSP, in short, automates the process of creating a virtual prototype, debugging software, and deploying the virtual prototype to the software team. This year, VSP was honored as an Ultimate Product in the EE Times/EDN ACE Awards.
Michael McNamara, vice president and general manager of system level design at Cadence, who accepted the award, talked with us during our road trip about the rationale behind developing VSP: