LEXINGTON, Mass.–Several years ago, an FPGA executive stood before industry colleagues and delivered one of the biggest FUD speeches you’ve ever heard.

It takes $50 million-$100 million today to develop a chip, he said. That chip, given traditional competitive situations, needed a billion-dollar end market to make any reasonable ROI. There aren’t that many billion-dollar end applications any more, so chip design, he intimated, was dead. Unless you used FPGAs, in which case, all was well.

More design resources

It does take a lot of money to design an SoC on a leading-edge process today, but it doesn’t have to cost $100 million, or even $10 million.

It can cost around $2 million, argues Andreas Olofsson, founder and CEO of Adapteva. His company’s Epiphany many-core processors have been done on 65nm and now 28nm for $2 million.

“You can spend $100 million on a very, very complicated SoC,” he said. “Apple certainly spent $100 million on the A5. IBM Cell was multiples of hundreds of millions of dollars for that consortium. It’s possible. But it doesn’t have to be.”

He continued: “How many features do you put in there, how big is the software stack and how well do you manage the process?”

At 65nm, Epiphany was 16 cores; Adapteva just this summer taped out 64 cores on Global Foundries’ 28nm process, 10mm^2. That’s an astonishing feat for $2 million.

Olofsson’s strategy is to offer the market a small, powerful but power-miserly (<2W power consumption) coprocessor to take the compute load off FPGAs (and other devices) for applications like face- and voice-recognition and other emerging media applications. The last key: make it C or C++ programmable.

The device can scale to thousands of cores and teraflops worth of performance, Olofsson said.

Here’s Olofsson on efficiently financing a powerful microprocessor:

Here’s Olofsson describing the Epiphany device: